1. Field of the Invention
The present invention relates to a test pattern generating method, device, and program for the tests carried out on a tester which judges non-defectiveness/defectiveness of a manufactured LSI (Large Scale Integrated circuit) and particularly relates to a test pattern generating method, device, and program for the tests used in non-defectiveness/defectiveness judgement of an LSI having a plurality of common circuits like a multi-core processor.
2. Description of the Related Arts
Conventionally, in the last process of the manufacturing processes of an LSI, a test operation is carried out by using test patterns on the tester for judging non-defectiveness/defectiveness of the manufactured LSI. Generally, an automatic test pattern generation system (Automatic Test Pattern Generation system: hereinafter, referred to as “ATPG”) is used for the test patterns used in the non-defectiveness/defectiveness judgement of the LSI. In such an ATPG system, examples of main functions include:
(1) circuit-model reading and writing functions,
(2) an automatic test pattern generating function of generating a test pattern for one given fault,
(3) a static or dynamic compaction function of compacting the test patterns created by ATPG, and
(4) a fault simulator function of evaluating generated tests.
    [Patent Document 1] Japanese Laid-open Patent Publication No. 63-75973    [Patent Document 2] Japanese Laid-open Patent Publication) No. 2005-174112Incidentally, in recent processor designing, a multi-core processor technique which enhances performance by providing a plurality of core units in one LSI and causing the cores to carry out parallel operations attracts attention. When test patterns are to be generated for such a multi-core processor, in a conventional system, if some sorts of restriction conditions are not given, ATPG is executed for all the assumed faults which can be achieved at a certain point. Therefore, increase in the circuit size due to pluralization of cores causes a problem that the assumed faults for which ATPG is executed are increased, in other words, test generation time is increased simply in proportion to the number of the cores. The increase in the number of cores does not only affect the increase in the test generation time, but also causes a problem of increase in the amount of test vectors (the amount of data used for evaluating whether a circuit satisfies designed specifications or not) which are necessary in tests.